(1) Field of the Invention
The present invention relates to a self-diagnosable semiconductor memory device having a redundant circuit, and particularly, relates to a semiconductor memory device which can be combined with a random logic circuit into a single package in such a form that the semiconductor memory cannnot be directly accessed from outside of the package, and a semiconductor apparatus having the semiconductor memory in such form.
(2) Description of the Related Art
The scale of a semiconductor memory devices has become larger and larger in recent years, and production yield and reliabilty are required to be further improved.
For improving the production yield, there is a method in which a redundant circuit is provided in the semiconductor memory device, and, when defective portions are detected in a normal circuit portion, each defective portion is replaced with a portion of the redundant circuit having the same function. In this way, the production yield is improved because each produced device having at least one defect in the normal circuit portion, which would have been discarded in the past, can be changed to a functioning apparatus.
The semiconductor memory device has a constitution in which word lines and bit lines (or pairs of bit lines) are arranged in a lattice and memory cells are arranged at intersections of the word lines and the bit lines, and each memory cell can be accessed by selectively activating word lines and bit lines. The redundant circuit for replacing defective memory cells generally has a constitution in which each replacement is carried out by a unit of a word line or a bit line. Therefore, all memory cells connected to the word line or the bit line to which each defective memory cell is connected are simultaneously replaced. Namely, the replacement of each defective memory cell is carried out by a row or a column of the memory cell matrix. The redundant circuit is composed of the redundant memory cell arrays and a redundant switching circuit which switches the redundant memory cell arrays to be accessed when the replaced rows or columns of the normal memory cells are accessed.
In one known switching method in the redundant switching circuit, positions of the replaced rows or columns are stored, and, when an address comparing circuit detects the replaced rows or columns to be accessed by comparing an address signal with the stored positions, the replaced rows or columns are controlled so as not to be accessed and the redundant memory cell arrays are controlled to be accessed by the address comparing circuit. In another known switching method in the redundant switching circuit, lines from a row decoder or a column decoder to the replaced word lines or bit lines are cut off, and the redundant memory cell arrays are connected to corresponding positions of the row decoder or the column decoder. Alternatively, in other types of redundant switching circuits, the storage of the replaced rows or columns, and the cutting and the connecting of lines are carried out by fusing of fuse circuits or laser trimming operations.
In order to replace defective memory cells, the existence of defective memory cells needs to be detected, and, when defective memory cells exist, the positions of the defective memory cells need to be detected. The positions of the word lines connected to the defective memory cells must be detected when the replacing operation is carried out by a word line, and the positions of the bit lines connected to the defective memory cells must be detected when the replacing operation is carried out by a bit line. In an operation to detect positions of the defective memory cells, by sequentially changing an address signal applied to address terminals of the memory, predetermined data is written into each memory cell and is read from the memory cell, and it is confirmed whether the read data coincides to the written data. When the read data does not coincide to the written data, the memory cell is judged to be defective, and the address of the memory cell is stored. The replacement with the redundant circuit is carried out by using the laser trimming operation and so forth according to the determined positions of the defective memory cells. Consequently, in the normal memory test of the prior art, the memory device is operated from outside via input/output (I/O) terminals, and outputs of the memory device are checked outside. In this way, positions of the defective memory cells are detected.
Japanese Unexamined Patent Publication (Kokai) No.4-132095 discloses a test apparatus of a memory device in which defective memory cells are replaced with a redundant circuit by a unit of a row or a column.
Japanese Unexamined Patent Publication (Kokai) Nos.60-254499 and 64-55799 disclose semiconductor memory devices in which the positions of the defective memory cells replaced with the redundant circuit can be read from outside of the devices.
The semiconductor memory device disclosed in Japanese Unexamined Patent Publication (Kokai) Nos.64-55799 includes a programmable ROM for storing positions of word lines or bit lines connected to defective memory cells replaced with the redundant circuit, and contents of the programmable ROM can be output to address terminals. In this way, a user can also detect positions of the replaced memory cells from outside of the device.
In the semiconductor memory devices disclosed in the above documents, the positions of the defective memory cells replaced with the redundant circuit can be read out to outside. However, every operation of the memory test for replacing defective memory cells with the redundant circuit, which include an application of an address signal for accessing each memory cell, is carried out from outside of the device via terminals. An operation of comparing the written data and the read data is also carried out outside of the device. Therefore, the semiconductor memory device needs to be directly accessable from outside.
Further, in order to improve reliability of the memory device, a self-diagnostic circuit is implemented into the memory device, which detects the occurrence of defective memory cells after the device is embedded into an apparatus. In a test carried out by the self-diagnostic circuit, after predetermined data is written into every memory cell, stored data is read out from every memory cell and it is judged whether or not the read data coincides with the written data. When a defective memory cells exist, the self-diagnostic circuit reports the existence of the defective memory cells. Therefore, this test of the self-diagnostic circuit is similar to the test for replacing defective memory cells with the redundant circuit, however, information relating to positions of the defective memory cells is not output in this test of the self-diagnostic circuit. The reason this information is not output is that, since defective memory cells newly generated after the completion of the device cannot be replaced with the redundant circuit, the self-diagnostic circuit only needs to output information relating to an existence of defective memory cells.
Japanese Unexamined Patent Publications (Kokai) No.64-55799 discloses a semiconductor memory device which includes redundant memory cells, a selection circuit for selecting the redundant memory cells, and a self-testing circuit. This memory device can relieve problems caused by defective memory cells generated after completion of a device. However, a defective memory cell address storage circuit which can store the addresses of the defective memory cells after the completion of the device needs to include a programmable ROM. Since the area of the programmable ROM is larger than that of a storage circuit trimmed by a laser beam, a problem that the scale of the device becomes large occurs. Further, since a high voltage which is not used in a normal mode is required to write data into the programmable ROM, the high voltage must be supplied from outside or a booster circuit needs to be implemented in the memory device. When the high voltage is supplied from outside, an apparatus using the memory device needs a high voltage source. When the high voltage is supplied from the booster circuit implemented in the memory device, the memory device becomes large and complicated.
Further, in recent years, a semiconductor device in which a random logic device and a memory device are combined together in a same package is used. In this type semiconductor device, the memory device cannot be accessed from outside. The memory capacity of the memory device implemented in this type of device has recently become larger and larger. Therefore, in this type of memory device, the redundant circuit is also implemented in order to improve the production yield, and the self-diagnostic circuit is also implemented in order to increase reliablity.
As described above, since the memory device cannot be accessed from outside, the memory test for replacing defective memory cells with the redundant circuit cannot be carried out via I/O terminals of the semiconductor device. Of course, the number of the I/O terminals of the semiconductor device is limited, therefore, I/O terminals to directly access the implemented memory device cannot be increased. In a known semiconductor device of this type, a plurality of electrode pads which are not connected to the I/O terminals are arranged in the device, and the memory test is carried out by contacting probes of the testing apparatus to the electrode pads. However, in this device, the semiconductor device becomes large, complicated and expensive since the electrode pads have large areas and the amount of wiring increases. In another known semiconductor device of this type, a switching circuit which switches wiring between the random logic device and the memory device to be connected to the I/O terminals only when the memory test is carried out is provided. However, in this device, the switching circuit needs to be further implemented, and the amount of wiring increases. Therefore, the semiconductor device also becomes large, complicated and expensive. This problem is difficult to overcome when the number of the electrode pads increases.